RISC-V Processor Design – Lec 6 – EXU and Co-Simulation
Lecture here: https://youtu.be/lI5qD1PkHtA
In this lecture, we stitch together a custom Instruction Set Simulator I created with the RISC-V CPU (now with the execution stage) and see the first instructions flowing in the pipeline.
We wrap up the lecture with a minor bug-fixing session, during which I will walk you through using the ISS logs to debug issues quickly.